1. Field of the Invention
This invention relates to a semiconductor integrated circuit, and more particularly to a substrate potential controlling circuit used in a semiconductor integrated circuit.
2. Description of the Related Art
A semiconductor integrated circuit generally includes a substrate potential controlling circuit for reducing current consumption caused by operation of a substrate potential generating circuit itself.
In general, such a substrate potential controlling circuit includes a substrate potential generating circuit for generating a substrate potential, a substrate potential detecting circuit for detecting the substrate potential, and a switching circuit for ON-OFF controlling the operation of the substrate potential generating circuit according to the output of the substrate potential detecting circuit. With the substrate potential controlling circuit, when the substrate potential is lowered and reaches a preset level, the substrate potential detecting circuit detects that the substrate potential is set to the preset value and supplies a detection output to the switching circuit. The switching circuit interrupts the operation of the substrate potential generating circuit in response to the detection output. In this way, the substrate potential generating circuit will not consume any current if the substrate potential is set below the threshold value of the substrate potential detection circuit. The substrate potential controlling circuit can keep the substrate potential at a constant level without increasing the current consumption by use of the above feedback loop.
The above substrate potential controlling circuit has a defect that the substrate potential cannot be controlled at a sufficiently high speed in response to variations in the power source voltage. Therefore, a substrate potential controlling circuit which can control the substrate potential irrespective of variations in the power source voltage has been developed. Such a circuit is disclosed in U.S. Pat. No. 4,794,278 (Inventor: Branislav, Vajdic, Applicant: Intel Corporation, Patented Date: Dec. 27th, 1988). The substrate potential controlling circuit disclosed in the above U.S. Patent includes first and second level detectors. The first level detector detects a substrate voltage less negative than a preset value. At this time, it supplies charges by use of the charge pump to force the substrate to a more negative voltage level. When the substrate voltage exceeds the threshold value, the charge supply is interrupted. The second level detector becomes operative when the substrate voltage has exceeded a preset limit level which lies on the negative side with respect to the threshold value. At this time, a clamper is operated to clamp the substrate voltage.
However, if the second detector is provided as described above, the total power consumption is increased by the power consumption of the second detector and therefore it is impossible to use the second detector in a device which requires a low power consumption. Further, since the detection circuit is separately disposed, the substrate potential may not be precisely controlled if the characteristics of detection elements are not constant.